High-speed data communication systems frequently rely on clock and data recovery (CDR) circuits within the receiver rather than transmitting a reference clock with the data. For example, serial data communication may include the use of a serializer-deserializer (SERDES) at each end of a communication link. Within a SERDES, a CDR may extract a clock that is embedded in the incoming data stream. Once a clock is recovered, the clock is used to sample the incoming data stream to recover individual bits.
During propagation, data signals may experience distortion through the bandwidth-limited transmission channel. The distortion can result in spreading of signal pulse energy from one symbol period to another. The resulting distortion is known as inter-symbol interference (ISI). In general, ISI becomes worse as the speed of the communication system increases. As a result, high-speed communication systems often incorporate circuitry to equalize the effects of ISI. One technique involves use of a decision feedback equalizer (DFE) in the receiver. A DFE in the receiver can mitigate post-cursor ISI (i.e., the spreading of a previous symbol into a current symbol). Another technique involves use of a feed forward equalizer (FFE) in the transmitter to equalize the signal prior to transmission through the channel. An FFE can mitigate pre-cursor ISI (i.e., the spreading of a future symbol into a current symbol).
Loss-of-signal detection is required for some communication systems. One technique for detecting loss-of-signal is use of an analog envelope detector in the receiver to detect signal magnitude, which depends on data rate and channel loss. If the detection threshold of the envelope detector is too high, there is a risk of false loss-of-signal detection. Thus, design of a low-threshold envelope detector that operates reliably at high speeds is challenging.